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1/21 october 2003 rev. 3.4 m48z128 m48z128y, M48Z128V* 5.0v or 3.3v, 1 mbit (128 kbit x 8) zeropower ? sram * contact local sales office features summary n integrated, ultra low power sram, power-fail control circuit, and battery n conventional sram operation; unlimited write cycles n 10 years of data retention in the absence of power n battery internally isolated until power is first applied n automatic power-fail chip deselect and write protection n write protect voltages: (v pfd = power-fail deselect voltage) C m48z128: v cc = 4.75 to 5.5v 4.5v v pfd 4.75v C m48z128y: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v C M48Z128V: v cc = 3.0 to 3.6v 2.8v v pfd 3.0v n soic package provides direct connection for a snaphat top which contains the battery n snaphat housing (battery) is replaceable n pin and function compatible with jedec standard 128k x 8 srams n equivalent surface-mount (smt) solution requires a 28-pin m40z300/w and a stand-alone 128k x8 lpsram (snaphat ? top to be ordered separately) figure 1. 32-pin pmdip module pmdip32 (pm) module 32 1
m48z128, m48z128y, M48Z128V* 2/21 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 logic diagram (figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 signal names (table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 dip connections (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 block diagram (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 hardware hookup for equivalent surface-mount (smt) solution (figure 5.) . . . . . . . . . . . . . . . . . . 5 equivalent surface-mount (smt) solution (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operating and ac measurement conditions (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ac measurement load circuit (figure 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 capacitance (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc characteristics (table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating modes (table 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chip enable or output enable controlled, read mode ac waveforms (figure 7.). . . . . . . . . . . . . 9 address controlled, read mode ac waveforms (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read mode ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write enable controlled, write ac waveforms (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chip enable controlled, write ac waveforms (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write mode ac characteristics (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power down/up mode ac waveforms (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power down/up ac characteristics (table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power down/up trip points dc characteristics (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 v cc noise and negative going transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 supply voltage protection (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 snaphat battery table (table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21 m48z128, m48z128y, M48Z128V* description the m48z128/y/v zeropower ? ram is a 128 kbit x 8 non-volatile static ram organized as131,072 words by 8 bits. the device combines an internal lithium battery, a cmos sram and a control circuit in a plastic, 32-pin dip module. this solution is available in two special packages to provide a highly integrated battery backed-up memory solution. the m48z128/y/v is a non-volatile pin and func- tion equivalent to any jedec standard 128k x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 32-pin, 600mil dip module houses the m48z128/y/v sili- con with a long life lithium button cell in a single package. for surface-mount environments st provides an equivalent smt solution consisting of a 28-pin, 330mil soic nvram supervisor (m40z300/ w) and a 32-pin, (tsop, 8 x 20mm) 1mb lpsram. both 5v and 3v versions are available (see table 2, page 5). the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery. the unique design allows the snaphat battery package to be mounted on top of the soic pack- age after the completion of the surface-mount pro- cess. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the snaphat battery package is shipped sepa- rately in plastic anti-static tubes or in tape & reel form. the part number is m4zxx-br00sh (see table 13, page 15). figure 2. logic diagram table 1. signal names ai01194 17 a0-a16 w dq0-dq7 v cc m48z128 m48z128y M48Z128V g v ss 8 e a0-a16 address inputs dq0-dq7 data inputs / outputs e chip enable input g output enable input w write enable input v cc supply voltage v ss ground nc not connected internally
m48z128, m48z128y, M48Z128V* 4/21 figure 3. dip connections figure 4. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a16 nc v cc ai01195 m48z128 m48z128y M48Z128V 10 1 2 5 6 7 8 9 11 12 13 14 15 16 30 29 26 25 24 23 22 21 20 19 18 17 a12 a14 w nc 3 4 28 27 32 31 ai01196 internal battery e v cc v ss voltage sense and switching circuitry 131,072 x 8 sram array a0-a16 dq0-dq7 w g power e
5/21 m48z128, m48z128y, M48Z128V* figure 5. hardware hookup for equivalent surface-mount (smt) solution note: for pin connections, see individual data sheet for m48z300/300w at www.st.com. 1. connect ths pin to v out if 4.2v v pfd 4.5v (m48z128y) or connect ths pin to v ss if 4.5v v pfd 4.75v (m48z128). 2. connect ths pin to v ss if 2.8v v pfd 3.0v (M48Z128V). 3. snaphat ? top ordered separately. table 2. equivalent surface-mount (smt) solution note: 1. connection of threshold select pin (pin 13) of supervisor (m40z300/300w). nvram lpsram supervisor ths pin (1) m48z128 5v 1mb lpsram m40z300 v ss m48z128y 5v 1mb lpsram m40z300 v out M48Z128V 3v 1mb lpsram m40z300w v ss ai03625 e1 con v ss v out ths (1,2) a m40z300/w e b e2 con e3 con e4 con v ss e2 v cc 1mb lpsram e a0-a16 w dq0-dq7 snaphat battery (3) rst bl
m48z128, m48z128y, M48Z128V* 6/21 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 3. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package: reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t bias temperature under bias C10 to 70 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7 v v cc supply voltage m48z128/y C0.3 to 7.0 v M48Z128V C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
7/21 m48z128, m48z128y, M48Z128V* dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 6. ac measurement load circuit note: 1. 50pf for M48Z128V (3.3v). table 5. capacitance note: 1. effective capacitance measured with power supply at 5v (m48z128/y) or 3.3v (M48Z128V); sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m48z128/y M48Z128V unit supply voltage (v cc ) 4.75 to 5.5v or 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai03630 c l = 100pf or 50pf (1) c l includes jig capacitance 650 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
m48z128, m48z128y, M48Z128V* 8/21 table 6. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). 2. outputs deselected. operating modes the m48z128/y/v also has its own power-fail de- tect circuit. the control circuitry constantly moni- tors the single v cc supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low v cc . as v cc falls below the switchover voltage (v so ), the control cir- cuitry connects the battery which maintains data until valid power returns. table 7. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 11, page 14 for details. sym parameter test condition (1) m48z128/y M48Z128V unit C70 / C85 / C120 C85 / C120 min max min max i li input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i cc supply current e = v il outputs open 105 50 ma i cc1 supply current (standby) ttl e = v ih 74ma i cc2 supply current (standby) cmos e = v cc C 0.2v 43ma v il input low voltage C0.3 0.8 C0.3 0.6 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh = C1ma 2.4 2.2 v mode v cc e g w dq0-dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
9/21 m48z128, m48z128y, M48Z128V* read mode the m48z128/y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 1,048,576 locations in the static storage array. thus, the unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g (output enable) access times are also sat- isfied. if the e and g access times are not met, val- id data will be available after the later of chip enable access time (t elqv ) or output enable ac- cess time (t glqv ). the state of the eight three- state data i/o signals is controlled by e and g . if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e and g remain low, output data will remain valid for output data hold time (t axqx ) but will go indeter- minate until the next address access. figure 7. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high. figure 8. address controlled, read mode ac waveforms note: chip enable (e ) and output enable (g ) = low, write enable (w ) = high. ai01197 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a16 e g dq0-dq7 valid ai01078 tavav tavqv taxqx a0-a16 dq0-dq7 valid data valid
m48z128, m48z128y, M48Z128V* 10/21 table 8. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). 2. c l = 5pf. symbol parameter (1) m48z128/y m48z128/y/v m48z128/y/v unit C70 C85 C120 min max min max min max t avav read cycle time 70 85 120 ns t av qv address valid to output valid 70 85 120 ns t elqv chip enable low to output valid 70 85 120 ns t glqv output enable low to output valid 35 45 60 ns t elqx (2) chip enable low to output transition 5 5 5 ns t glqx (2) output enable low to output transition 3 3 3 ns t ehqz (2) chip enable high to output hi-z 30 35 45 ns t ghqz (2) output enable high to output hi-z 20 25 35 ns t axqx address transition to output transition 5 5 10 ns
11/21 m48z128, m48z128y, M48Z128V* write mode the m48z128/y/v is in the write mode whenev- er w and e are active. the start of a write is ref- erenced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for minimum of t ehax from e or t whax from w prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx or t ehdx afterward. g should be kept high during write cycles to avoid bus con- tention; although, if the output bus has been acti- vated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. figure 9. write enable controlled, write ac waveforms note: output enable (g ) = high. figure 10. chip enable controlled, write ac waveforms note: output enable (g ) = high. ai01198 tavav twhax tdvwh data input a0-a16 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01199 tavav tehax tdveh a0-a16 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
m48z128, m48z128y, M48Z128V* 12/21 table 9. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v, 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48z128/y m48z128/y/v m48z128/y/v unit C70 C85 C120 min max min max min max t avav write cycle time 70 85 120 ns t avwl address valid to write enable low 0 0 0 ns t avel address valid to chip enable low 0 0 0 ns t wlwh write enable pulse width 55 65 85 ns t eleh chip enable low to chip enable high 55 75 100 ns t whax write enable high to address transition 5 5 5 ns t ehax chip enable high to address transition 15 15 15 ns t dvwh input valid to write enable high 30 35 45 ns t dveh input valid to chip enable high 30 35 45 ns t whdx write enable high to input transition 0 0 0 ns t ehdx chip enable high to input transition 10 10 10 ns t wlqz (2,3) write enable low to output hi-z 25 30 40 ns t av wh address valid to write enable high 65 75 100 ns t av eh address valid to chip enable high 65 75 100 ns t whqx (2,3) write enable high to output transition 5 5 5 ns
13/21 m48z128, m48z128y, M48Z128V* data retention mode with valid v cc applied, the m48z128/y/v oper- ates as a conventional bytewide ? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self t wp after v cc falls below v pfd . all outputs become high impedance, and all inputs are treated as don't care. if power fail detection occurs during a valid ac- cess, the memory cycle continues to completion. if the memory cycle fails to terminate within the time t wp , write protection takes place. when v cc drops below v so , the control circuit switches power to the internal energy source which preserves data. the internal coin cell will maintain data in the m48z128/y/v after the initial application of v cc for an accumulated period of at least 10 years when v cc is less than v so . as system power returns and v cc rises above v so , the battery is discon- nected, and the power supply is switched to exter- nal v cc . write protection continues for t er after v cc reaches v pfd to allow for processor stabiliza- tion. after t er , normal ram operation can resume. for more information on battery storage life refer to the application note an1012. figure 11. power down/up mode ac waveforms table 10. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time m48z128/y 10 s M48Z128V 150 t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t wp write protect time m48z128/y 40 150 s M48Z128V 40 250 t er e recovery time 40 120 ms ai01031 v cc e (per control input) outputs don't care high-z tf tfb tr trb twp tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so ter
m48z128, m48z128y, M48Z128V* 14/21 table 11. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5v, 4.5 to 5.5v, or 3.0 to 3.6v (except where noted). 3. at 25c; v cc = 0v. v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (see figure 12) is recommended in order to provide the needed fil- tering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recommends connecting a schottky diode from v cc to v ss (cathode con- nected to v cc , anode to v ss ). (schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface-mount). figure 12. supply voltage protection symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage m48z128 4.5 4.6 4.75 v m48z128y 4.2 4.3 4.5 v M48Z128V 2.8 2.9 3.0 v v so battery back-up switchover voltage m48z128/y 3.0 v M48Z128V 2.5 v t dr (3) expected data retention time 10 years ai02169 v cc 0.1 m f device v cc v ss
15/21 m48z128, m48z128y, M48Z128V* part numbering table 12. ordering information scheme note: 1. contact local sales office 2. the soic package (soh28) requires the battery package (snaphat ? ) which is ordered separately under the part number m4zxx-br00sh in plastic tube or m4zxx-br00shtr in tape & reel form. caution : do not place the snaphat battery package m4zxx-br00sh in conductive foam as it will drain the lithium button-cell bat- tery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 13. snaphat battery table example: m48z 128y C70 pm 1 device type m48z supply voltage and write protect voltage 128 = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 128y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 128v (1) = v cc = 3.0 to 3.6v; v pfd = 2.8 to 3.0v speed C70 = 70ns (for m48z128/y) C85 = 85ns (for m48z128/y/v) C120 = 120ns (for m48z128/y/v) package (2) pm = pmdip32 temperature range 1 = 0 to 70c part number description package m4z28-br00sh lithium battery (48mah) snaphat sh m4z32-br00sh lithium battery (120mah) snaphat sh
m48z128, m48z128y, M48Z128V* 16/21 package mechanical information figure 13. pmdip32 C 32-pin plastic dip module, package outline note: drawing is not to scale. table 14. pmdip32 C 32-pin plastic dip module, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.365 0.375 a1 0.38 C 0.015 C b 0.43 0.59 0.017 0.023 c 0.20 0.33 0.008 0.013 d 42.42 43.18 1.670 1.700 e 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 ea 14.99 16.00 0.590 0.630 l 3.05 3.81 0.120 0.150 s 1.91 2.79 0.075 0.110 n32 32 pmdip a1 a l be1 d e n 1 ea e3 s c
17/21 m48z128, m48z128y, M48Z128V* figure 14. soh28 C 28-lead plastic small outline, battery snaphat, package outline note: drawing is not to scale. table 15. soh28 C 28-lead plastic small outline, battery snaphat, package mechanical data symbol mm inch typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n 28 28 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
m48z128, m48z128y, M48Z128V* 18/21 figure 15. sh C 4-pin snaphat housing for 48mah battery, package outline note: drawing is not to scale. table 16. sh C 4-pin snaphat housing for 48mah battery, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
19/21 m48z128, m48z128y, M48Z128V* figure 16. sh C 4-pin snaphat housing for 120mah battery, package outline note: drawing is not to scale. table 17. sh C 4-pin snaphat housing for 120mah battery, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
m48z128, m48z128y, M48Z128V* 20/21 revision history table 18. revision history date rev. # revision details may 1999 1.0 first issue 13-apr-00 2.0 document layout changed; surface-mount chip set solution added 20-jun-00 2.1 t glqx changed (table 8) 19-jul-00 2.2 M48Z128V added 14-sep-01 3.0 reformatted; added temperature information (table 5, 6, 8, 9, 10, 11) 07-nov-01 3.1 remove chipset option from ordering information (table 12) 20-may-02 3.2 modify reflow time and temperature footnotes (table 3) 18-nov-02 3.3 modifying smt solution text (figure 2, 5; table 2) 17-sep-03 3.4 remove references to m68zxxx (obsolete) parts (figure 5; table 2); update disclaimer
21/21 m48z128, m48z128y, M48Z128V* information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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